Hi! I'm RITABAN PAL.

Simple Voting MachineCheck out ↗

Verilog, Yosys, GTKWave

• Developed RTL code and completed functional verification using Verilator and Yosys.
• Currently performing physical design execution, floor planning, and DRC checks using OpenLane flow.

Design & implementation of RISC-V based SoC subsystem with AXI interconnect for embedded applicationsCheck out ↗

Verilog, Yosys, GTKWave, OpenLane

• Developing RTL code and functional verification using Verilator and Yosys.
• Will execute physical design, floor planning, and DRC checks using OpenLane and KLayout upon completion of the front-end design phase.

IPMC Sensor E-Tongue Interface

• Designed signal conditioning analog circuits (op-amps, active filters) to capture and amplify micro-volt sensor responses for ADC processing.
• Interfaced digitized sensor output with microcontrollers to convert chemical responses into actionable digital signals.
• Engineered a 3D-modeled hardware test setup utilizing stepper motors, motor drives, ultrasonic sensors, and aligned rack-and-pinion gear systems; currently developing the software interface for system integration.

Automatic Dustbin

• Engineered an automated waste management system utilizing an Arduino Uno, servo motors, and ultrasonic sensor.
• Programmed microcontroller logic to actuate the lid when an object is detected within a 30cm radius, implementing a 10-second automatic closure delay.
• Integrated a capacity-detection fail-safe that triggers an audio alert (buzzer) and disables the opening mechanism when the bin reaches maximum capacity.