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Hey, I'm RITABAN

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Electrical Engineer

Passionate about advancing semiconductor technology through innovative design and verification.

RP

My Professional Side

I'm an Electrical Engineering undergraduate and GATE 2026 qualifier with three years of industrial experience. My expertise lies in RTL design, functional verification, and RISC-V SoC architecture, driven by a commitment to excellence in hardware development and engineering solutions.

Email
ritabanpal2000@gmail.com
Location
Tarakeswar, Hooghly, West Bengal – 712301
Education
B.Tech in Electrical Engineering

Education

B.Tech in Electrical Engineering

MCKV Institute of Engineering
Oct 2023 – June 2027 (Pursuing)SGPA: 9.23

Diploma in Electrical Engineering

Ramakrishna Mission Shilpamandira
2018 – Sept 2021CGPA: 9.2

Higher Secondary (12th)

WBCHSE
May 201880.6%

Secondary (10th)

WBBSE
April 201689.28%

Skills

Skills

Languages
Cloud & DevOps
Other Technical Skills

Stuff I Built

S

Simple Voting Machine

Verilog, Yosys, GTKWave

  • Developed RTL code and completed functional verification using Verilator and Yosys.
  • Currently performing physical design execution, floor planning, and DRC checks using OpenLane flow.
VerilogYosysGTKWave
D

Design & implementation of RISC-V based SoC subsystem with AXI interconnect for embedded applications

Verilog, Yosys, GTKWave, OpenLane

  • Developing RTL code and functional verification using Verilator and Yosys.
  • Will execute physical design, floor planning, and DRC checks using OpenLane and KLayout upon completion of the front-end design phase.
VerilogYosysGTKWaveOpenLane
I

IPMC Sensor E-Tongue Interface

  • Designed signal conditioning analog circuits (op-amps, active filters) to capture and amplify micro-volt sensor responses for ADC processing.
  • Interfaced digitized sensor output with microcontrollers to convert chemical responses into actionable digital signals.
  • Engineered a 3D-modeled hardware test setup utilizing stepper motors, motor drives, ultrasonic sensors, and aligned rack-and-pinion gear systems; currently developing the software interface for system integration.
A

Automatic Dustbin

  • Engineered an automated waste management system utilizing an Arduino Uno, servo motors, and ultrasonic sensor.
  • Programmed microcontroller logic to actuate the lid when an object is detected within a 30cm radius, implementing a 10-second automatic closure delay.
  • Integrated a capacity-detection fail-safe that triggers an audio alert (buzzer) and disables the opening mechanism when the bin reaches maximum capacity.

Work Experience

RISE Fellowship

RISC-V for Indian Semiconductor Education

Pursuing intensive training in logic design, Verilog programming, and RISC-V processor architecture. Designing and simulating hardware modules including multiplexers, adders, multipliers, and flip-flops. Developing in-order and out-of-order pipelines, optimizing memory hierarchies and cache performance, and implementing control logic for processors. Applying theoretical knowledge to practical RTL and system-level designs, enhancing problem-solving and analytical skills. Collaborating in a lab setting to execute complex digital design projects, demonstrating strong critical thinking and teamwork.

Aug 2026 – Present

Summer Intern

NIELIT & eChipHub

Participated in an intensive eight-week technical program focused on semiconductor fundamentals and advanced VLSI technologies. Developed industry-relevant skills in hardware design to support a direct transition into digital circuit design and RTL engineering. Created RTL code and performed comprehensive functional verification utilizing Verilator and Yosys. Executed physical design, floor planning, and design rule checks (DRC) using the OpenLane flow.

June 2026 – August 2026

Junior Electrical Engineer

Larsen & Toubro (L&T Construction) - TIIC-MABP Project · Assam

Executed electrical equipment maintenance, circuit design, and technical troubleshooting across large-scale industrial projects. Integrated sensor networks (RTD, Proximity, Loadcell) and pneumatic systems into Siemens PLC-driven automated control loops. Redesigned winch panel controls with Variable Frequency Drives (VFDs), achieving a 30% reduction in fuel consumption. Designed conveyor and cement feeding pump panels, saving ₹6 Lakhs compared to standard market procurement costs. Implemented an automatic lighting system in the workplace, reducing manpower requirements by up to 3%. Developed a solar electric vehicle for material and human transportation, reducing transit time and increasing productivity by up to 25%.

October 2021 – October 2024

Certifications

Qualified GATE 2026 in Electrical Engineering

Achieved 2nd Runner-Up in the IPMC-based E-Tongue System Poster Competition

NPTEL Certifications: VLSI Design Flow (RTL to GDSII), Hardware Modelling using Verilog, Digital Circuits

NPTEL

Bootcamp 2.0 - NIELIT: RTL, IP Integration & SoC signoff (30 Hours)

NIELIT
PCB Design - Pantech.AI: Designed 8085 microprocessor

PCB Design - Pantech.AI: Designed 8085 microprocessor

Pantech.AI
View →

Interests

Making & developing new technologiesPlaying VolleyballPlaying GuitarListing music

Say Hi, Don't Be Shy

Let's discuss your next project or just say hello!

Email
ritabanpal2000@gmail.com
Phone
+91-6296988488
Location
Tarakeswar, Hooghly, West Bengal – 712301
Connect With Me
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